Digital counter circuits, as the name implies, are used to count pulses of a binary input signal such as a clock signal. Typically, a counter circuit also receives an enabling or gating signal for enabling the counter to count during a predetermined interval. At the end of the counting interval, the counter is disabled and its cumulative count is latched to provide a count for the interval.
Counters can detect the count pulse from one of several events in an input signal. They may be sensitive either to the positive- or negative-going transition of the pulse edge or to the voltage level of the pulse. Both methods have a significant margin of error because they count each event as a complete clock cycle and do not resolve the cycle into only those portions present during the counting interval. For example, a positive transition edge-sensitive counter will count the same number of pulses regardless of whether the counting interval began before or after the negative-going transition of a pulse, because the negative-going transition is not detected by the counter. The interval is half a clock cycle longer in the first case than in the second case. It is desirable in many circumstances for the counter to resolve between portions of a clock cycle to provide a more accurate count, such as a fractional count of the cycles received during the interval.
Another drawback of counters that count only a single event in each clock cycle is the rate at which they count. The counter is limited by the frequency of the incoming signal.
One technique for increasing the resolution of digital counters is to utilize two independent counters in combination with a dual phase clock. Each counter receives a clock signal 180.degree. out of phase from the other signal, effectively doubling the counting rate. The outputs of each counter are then combined via logic circuitry to provide the total count. The obvious drawback of this technique is the high cost and complexity of the necessary circuit.